I'm looking to include JTAG testing in my circuit boards. I already have three JTAG compliant ICs on my boards:
1) AT Mega 128L (boundary scanning for this device is not 100% supported, I believe)
2) Two Altera Max V CPLDs.
I will have two JTAG headers on my board, one for programming the CPLDs and the other for programming the uC. My question is, how can I incorporate boundary scanning? What software do I need? I think, hardware wise, I only need to link the ICs in a daisy chain.
Finally, is this feasible on a small run of boards (around 100 in total)?