Incorporating Boundary-Scan/JTAG into a PCB

I'm looking to include JTAG testing in my circuit boards. I already have three JTAG compliant ICs on my boards:

1) AT Mega 128L (boundary scanning for this device is not 100% supported, I believe)

2) Two Altera Max V CPLDs.

I will have two JTAG headers on my board, one for programming the CPLDs and the other for programming the uC. My question is, how can I incorporate boundary scanning? What software do I need? I think, hardware wise, I only need to link the ICs in a daisy chain.

Finally, is this feasible on a small run of boards (around 100 in total)?

Hello there,

The good news for you is that the hard work has been done by Atmel and Altera - they put boundary-scan in their chips.

All you need is software to get your netlist and models (from Altera/Atmel) to test the nets.

There are a number of boundary-scan tools on the market that will meet your needs.

some of them are even free (so you can have a play before spending too much time/money!).

Have a look at "buzz" from JTAG Technologies (available from www.jtaglive.com).

You can use this to talk to the boundary-scan devices (read their ID's) before testing the interconnects.

It also supports Altera byteblaster cables so you should be set up and ready to go.

More information on how to set up a board for boundary-scan testing is available from here :

http://www.jtag.com/en/Learn/Boundary-scan_tutorial?session=hs2l4auob3vgcclteioqm3k6h0

I hope this helps but do feel free to contact me should you need anything.

Good luck !

Thank you VERY much! This cleared up a lot of things. Just one question: if I already have a JTAG header on my board, intended for programming purposes, I can use the SAME header for boundary-scanning?