This is my 2nd ever attempt at a layout and my first at a 4-layer one. I'm looking for some feedback because I'm sure I made some mistakes somewhere. It's not really a high-speed board, I'd be happy with 500kHz to 1MHz in performance as the speed of the electronics isn't the limiting factor.
Some info about the board: This is a wiring harness continuity checker. A test-vector is passed to the output banks and read back from the input side. The output has MOSFETs for buffers and the input has TVS diodes for ESD protection. U1 and U3 are Altera CPLDs and U5 is an AT Mega 128L. The connector towards the right is for a 6" 320x240 monochrome LCD. The chips between that connector and the uC are for level-translation. They may not be needed but that's something I need to test.
Each chip has 0.1uF X7R caps for every Vcc/GND pair. There's also 47uF bulk capacitance (tantalum caps) for each CPLD and finally 1000uF caps. Power is not going be regulated on this board - instead, that's a seperate PCB which regulates 1.8V, 3.3V and 5V. All regulators are linear. The power connector is polarized so there's no chance that 1.8V can be plugged into 3.3V or into Gnd.
It's not obvious from the picture, but the ground plane and the Vcc plane are completely unbroken. There are no traces going through them and I'm hoping this will help in performance. There are two buses on the board, SPI and JTAG. Both of these buses have non-inverting buffers and termination resistances in order to not have reflections as they go to multiple devices.
What do you think guys? I'm supposed to have this ready by Monday and I just have to add an oscillator and that's about it. I think I'm done unless there's a major change I have to make. Would really like opinions regarding the layout. Here's a view in 3D to give some perspective: